1. Technical Field
The present disclosure relates to a semiconductor memory device and a method of testing the semiconductor memory device and, more particularly, a semiconductor memory device capable of detecting a bridge defect and a bridge defect detecting method performed in the semiconductor memory device.
2. Discussion of Related Art
As the integration of semiconductor memory devices increases, the sizes of circuits of the semiconductor memory devices decrease. Accordingly, in the formation of the circuits of a semiconductor memory device, a process margin decreases. Thus, the possibility that a bridge defect is generated between adjacent memory cells increases. A bridge defect denotes a phenomenon in which a leakage current is generated due to a formation of a undesired current path between adjacent memory cells. When a bridge defect is generated between adjacent memory cells, the data stored in the memory cells may be lost.
To detect such a bridge defect, a conventional semiconductor memory device enables sense amplifiers connected to memory cells, when a predetermined period of time has passed after storing data in the memory cells. Then, the conventional semiconductor memory device reads out the data stored in the memory cells and detects whether a bridge defect has been generated or not based on the read data.
While the sense amplifiers are being enabled, however, coupling may occur between bit lines connected to the sense amplifiers.
When a bridge defect and a coupling phenomenon occur simultaneously, the bridge defect cannot be properly detected. Furthermore, it is more deleterious when a bridge defect generated between memory cells connected to the same word line cannot be detected.